1. Field of the Invention
The present invention relates to a constant current circuit.
2. Description of the Related Art
A conventional constant current circuit is described. FIG. 13 is a diagram illustrating a conventional constant current circuit.
An increase in a current Iref that flows in a resistor 54 raises a voltage generated in the resistor 54 and accordingly raises the gate-source voltage of an NMOS transistor 52, with the result that the conductance of the NMOS transistor 52 is increased. This reduces the gate voltage of an NMOS transistor 53, which leads to a lower gate-source voltage of the NMOS transistor 53 and a smaller conductance of the NMOS transistor 53. The current Iref is therefore reduced. A reduction in the current Iref that flows in the resistor 54 increases the current Iref because of the similar operation of the NMOS transistor 52 and the NMOS transistor 53. The conventional constant current circuit keeps the current Iref constant by operating in the manner described above (see, for example, JP 06-132739 A (FIG. 12)).
In prior art, when the power supply voltage is given as VDD, the gate-source voltage of a PMOS transistor 51 is given as Vgsp, the drain-source voltage of the NMOS transistor 53 is given as Vdsn, and the gate-source voltage of the NMOS transistor 52 is given as Vgsn, the constant current circuit needs to satisfy the following Expression (31) in order to operate properly:VDD>|Vgsp|+Vdsn+Vgsn  (31)
From Expression (31), the power supply voltage VDD needs to be higher than 1.6 V in order for the constant current circuit to operate properly when, for example, the gate-source voltage |Vgsp| and the gate-source voltage Vgsn are each 0.7 V and the drain-source voltage Vdsn is 0.2 V. In other words, the minimum operating power supply voltage is 1.6 V.